1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, to an improvement for operating at higher speed a semiconductor memory device with a fast access mode such as a nibble mode.
2. Description of the Prior Art
Conventional dynamic MOSRAM (dynamic random access memory having MOS transistors as components) includes a dynamic MOSRAM comprising a fast serial access mode referred to as a nibble mode.
FIG. 1 is a schematic diagram showing a structure of a dynamic MOSRAM with a nibble mode.
In FIG. 1, the conventional dynamic MOSRAM comprises a memory cell array divided into four array regions 1a, 1b, 1c and 1d for storing information, an X decoder 2 for decoding an address signal from an address buffer 6 and selecting a single word line from the memory cell arrays 1a to 1d, and a Y decoder 3 for decoding the address signal from the address buffer 6 and selecting four bit lines from the memory cell arrays 1a to 1d. The address buffer 6 receiving an external address signal for transferring to the X decoder 2 and the Y decoder 3 the address signal excluding two bits from the received external address signals. As a result, a four-bit memory cell is simultaneously selected from the memory cell arrays 1a to 1d. The remaining two bits from the address buffer 6 are applied to a four-bit address decoder AD. The four-bit address decoder decodes a two-bit address from the address buffer 6 and renders one of four transfer gates G1, G2, G3 and G4 conductive (an ON state).
A data input/output system comprises first data input/output lines I/O1, I/O2, I/O3 and I/O4 for sending to and receiving from memory cell arrays 1a to 1d four-bit information in parallel, four preamplifiers PA1, PA2,
and PA4 connected to respective data input/output lines I/O1 to I/O4 for amplifying the applied information, second data input/output lines I/O1*, I/O2*, I/O3* and I/O4* for connecting respective preamplifiers PA1 to PA4 to a data input buffer 4 and a data output buffer 5 through the transfer gates G1, G2, G3 and G4, the data input buffer 4 responsive to an activating signal .phi..sub.W for sequentially transmitting data applied to a data input terminal D.sub.in, the data output buffer 5 responsive to the activating signal .phi..sub.O for sequentially transmitting data applied through any of the transfer gates G1 to G4 to a data output terminal D.sub.out and the transfer gates G1, G2, G3 and G4 responsive to a signal from the address decoder AD to be turned on.
The address decider AD comprises four decoders A1, A2, A3 and A4. In addition, the address decoder AD functions as a shift register. More specifically, when a CAS signal for providing timing of a strobe of a column address is rendered active (an L level) twice or more while a RAS signal for providing timing of a strobe of a row address is active (the L level), the contents of the decoders A1 to A4 are shifted to the adjacent decoders in response to the second and subsequent fall of the CAS0 signal. Thus, a transfer gate selected by the address decoder AD being turned on in response to the first fall of the CAS signal is turned off in response to the fall of the next CAS signal, so that the ON state of the first selected transfer gate is shifted to the adjacent transfer gate. In the nibble mode, the CAS signal is rendered active four times while RAS signal is active. Therefore, the four-bit memory cells are sequentially accessed in response to one addressing.
FIG. 2 is a waveform diagram showing operation of the semiconductor memory device shown in FIG. 1. In FIG. 2, signal waveforms N2 and N3 used in a read/write decision circuit as described below are also shown. In FIG. 2, the signal .phi..sub.W for activating the data input buffer 4 is not shown. However, the signal .phi..sub.W is shifted to an active state in response to the later active state of the active state of the CAS signal and the active state of a write enable signal for designating write/read operation. Referring now to FIGS. 1 and 2, description is made on operation at the time of reading (a WE signal remains at the H level).
The RAS0 signal falls to be rendered active, so that a row address RA1 is latched to the address buffer 6 and then, applied to the X decoder 2. Therefore, a single word line is selected from the memory cell arrays 1a to 1d. When the CAS signal falls to be rendered active, a column address CA1 is latched to the address buffer 6 and then, transferred to the Y decoder 3. The column address excluding two bits are transferred to the Y decoder 3 from the address buffer 6, and the remaining two bits are applied to each of the decoders A1 to A4 of the address decoder AD. As a result, the four-bit memory cells are selected by the Y decoder 3, so that information of the selected four-bit memory cells is applied to each of the preamplifiers PA1 to PA4. On the other hand, the address decoders A1 to A4 decode applied two-bit information and turn one of the transfer gates G1 to G4 on. Therefore, one of the preamplifiers PA1 to PA4 is connected to the input buffer 4 and the output buffer 5. Then, the signal .phi..sub.O is rendered active, the output buffer 5 is activated, and information of selected one of the preamplifiers PA1 to PA4 is applied to the output terminal D.sub.out through the output buffer 5 as output data after a lapse of a time period t.sub.A from the fall of the CAS signal. After the RAS signal is rendered active, a cycle which is started in response to the fall of the first CAS signal is always a normal cycle, so that a memory cell designated by an external address Ext. ADD is selected.
When the CAS signal rises once and falls again, the nibble mode is started. In the cycle, the contents of the address decoders A1 to A4 are shifted to adjacent address decoders in response to the second fall of the CAS signal. Accordingly, a transfer gate adjacent to the transfer gate which is first turned on is turned on, so that information of a corresponding preamplifier out of the preamplifiers PA1 to PA4 is applied to the output buffer 5. The signal .phi..sub.O is rendered active again, and information of an adjacent memory cell is transmitted to the output terminal D.sub.out through the output buffer 5 after a lapse of a time period t.sub.A.sup.* from the fall of the CAS signal. The access time t.sub.A.sup.* at hat time is much shorter than the access time t.sub.A at the time of the normal mode. When the operation is further repeated twice while the RAS signal is active, information of a memory cell designated by the external address signal and three-bit memory cells continuously adjacent to the memory cell are sequentially read out at high speed.
When data is written, the write enable signal WE is rendered active in the same manner as the CAS signal. Accordingly, the signal .phi..sub.W is rendered active, so that data from the data input terminal D.sub.in are sequentially written into the corresponding memory cells through the input buffer 4.
In data write operation, operation modes referred to as an early write mode and a delayed write mode are known.
In the early write mode, the WE signal falls (t.sub.WC &lt;0 in FIG. 2) before the CAS signal falls, data are not outputted to the data output terminal D.sub.out (a D.sub.out signal in a high impedance state), and data applied to the data input terminal D.sub.in are written into the corresponding memory cells in response to the fall of the CAS signal.
In the delayed write mode, after a lapse of a predetermined time period from the fall of the CAS signal (t.sub.WC &gt;0), the WE signal falls. Accordingly, the .phi..sub.W signal is rendered active. In the delayed write mode, valid data are outputted to the data output terminal D.sub.out from the data output buffer 5 and then, data applied to the data input terminal Din are written into a corresponding memory cell.
It is determined by the circuit shown in FIG. 3 whether or not the output of the output buffer 5 is rendered a high impedance state or a valid state.
FIG. 3 is a diagram showing a specific structure of a read/write decision circuit. In FIG. 3, the decision circuit comprises four-stage inverters 11a, 11b, 11c and 11d connected in series receiving the CAS signal for delaying the same by a predetermined time period .tau.1 and outputting the same, an inverter 11e receiving the WE signal for inverting and outputting the same, an NOR gate 12a receiving outputs of the inverter 11d and the inverter 11e, an NOR gate 12b having one input receiving an output of the NOR gate 12a and other input receiving a signal N2 of an output of an NOR gate 12c, the NOR gate 12c having one input receiving an output of an NOR gate 12b and other input receiving the CAS signal, an NAND gate 13 receiving an output (N2) of the NOR gate 12c and a signal N3, and an inverter 11f receiving an output of the NAND gate 13 for inverting the same to output the buffer activating signal .phi..sub.O.
The NOR gates 12b and 12c constitute a flip-flop. The signal N2 is at the L level when both the CAS signal and the WE signal are at the H level. The signal N3 is obtained by delaying the CAS signal by a predetermined time period and inverting the same. More specifically, at the time of the normal mode (the first cycle), the preamplifiers PA1 to PA4 operate, and the signal N3 rises after data are read put to an input portion of the output buffer 5. In addition, at the time of the nibble mode, the signal N3 rises immediately after the transfer gates G1 to G4 are switched in response to the fall of the CAS signal. Description is now made on operation.
While the CAS signal is at the H level, the signal N1 is at the H level. On the other hand, when the WE signal is at the H level, the output of the inverter 11e is at the L level. Thus, the output of the NOR gate 12a is at the L level at that time. In this state, since the output of the NOR gate 12c is at the L level and the signal N3 is also at the L level, the signal .phi..sub.O is at the L level.
When the CAS signal falls, the normal mode is started. The signal N1 falls after a lapse of the delay time .tau.1 from the fall of the CAS signal. At that time, if signal WE remains at the L level (in the read cycle), the output of the NOR gate 12a rises to the H level. The output state of the NOR gate 12c is inverted in response to the rise of the output of the NOR gate 12a, so that the signal N2 rises. Then, when the signal N3 rises after a lapse of a predetermined time period from the fall of the CAS signal, the output of the NAND gate 13 falls to the L level. Accordingly, the activating signal .phi..sub.O rises. Therefore, the output buffer 5 is activated, so that valid data are outputted to the output terminal D.sub.out from the output buffer 5. When the CAS signal rises and falls again, the nibble mode is started. At that time, in the same manner as the above described operation, the signal N2 falls after a lapse of the delay time .tau.1 from the fall of the CAS signal. On the other hand, at the time of the nibble mode, since the signal N3 rises immediately after the transfer gates G1 to G4 are switched, the signal N3 rises before the signal N2 rises. Thus, at the time of the nibble mode the signal .phi..sub.O rises immediately after a lapse of the delay time .tau.1 so that the output buffer 5 is activated.
On the other hand, at the time of the early write mode, the WE signal falls before the CAS signal falls. Thus, the output of the NOR gate 12a remains at the L level. Therefore, in this case, even if the CAS signal falls, the output of the NOR gate 12c remains at the L level. Thus, even if the signal N3 rises, the output of the NAND gate 13 remains at the H level. Accordingly, the signal .phi..sub.O attains the L level, so that the output buffer 5 is not activated. Therefore, in the early write mode, the output state of the output buffer 5 becomes the high impedance state, so that valid data are not read out. As a result, the early write mode and the write cycle mode can be differentiated. In the above described structure, at the time of the normal access mode, the rise of the signal .phi..sub.O is determined by the signal N3 which rises after the preamplifiers PA1 to PA4 operate and data are transmitted to the input portion of the output buffer. Thus, the delay time of the signal N3 with respect to the CAS signal determines the access time (the time required for activating the output buffer 5 from the fall of the CAS signal), so that the delay time .tau.1 of the signal N2 with respect to the CAS signal is not the access time. However, in the nibble mode, since the signal N3 rises immediately after the transfer gates G1 to G4 are switched, the rise of the signal .phi..sub.O is determined by the delay time .tau.1 of the signal N2 with respect to the CAS signal. Thus, the access time in the nibble mode is determined by the delay time .tau.1.
In practice, the delay time .tau.1 is increased to provide a margin for timing of the fall of the WE signal to perform early write operation at the time of the normal mode. Therefore, there is a problem that the access time in the nibble mode is longer than needed, due to the delay time of the read/write decision circuit.
A general structure and operation of the conventional semiconductor memory device comprising the nibble mode is described in U.S. Pat. No. 4,344,156, and a catalogue INMOS Inc. "100ns 64K Dynamic Ram Using Efficient Redundancy Techniques".